1. Field of the Invention
The present invention relates to integrated circuits and more particularly to gate arrays. Specifically, the present invention provides a method and apparatus for protecting gate electrodes of target transistors in the gate array from gate charging by employing free transistors in the gate array.
2. Description of the Related Art
A gate array or uncommitted logic array (ULA) is a simple form of large scale integration (LSI) logic. Gate arrays are an example of a larger category of circuit known as semi-custom integrated circuits. Gate arrays are manufactured by first employing a defined set of mask steps (i.e. masking levels used in the manufacturing of semiconductors) to create a basic array of cells (base array). This base array includes a predetermined set of unconnected transistors.
An additional defined set of mask levels are then employed to determine the overall function of the gate array. These additional mask levels are unique to a specific logical implementation (i.e., the functional application that is to be achieved) and interconnect the gate array transistors. The additional mask steps can be designed and applied to the standard gate array quickly and relatively inexpensively as compared to a full custom implementation of the same overall functional application.
Typically, gate array cells are laid out in a row and column fashion. Gate arrays can incorporate as many gate array cells as necessary to accomplish the functional application. Of course, as with all other Very Large Scale Integration (VLSI) design implementations, application specifications must warrant the use of the gate array methodology.
Semi-custom integrated circuits typically require multiple masking levels to make the transistors and other circuit elements for the semi-custom integrated circuits. These multiple masking levels are standardized and are independent of the final application (i.e. independent of the actual logic design). Since these multiple masking levels are standardized, the integrated circuit wafers can be processed in advance with the standard pattern levels.
Typically, additional pattern levels are then employed to determine the overall function of the gate array chip (i.e., to implement the logic design). These additional pattern levels, which are unique to the specific application, provide the desired interconnections. These additional pattern levels can be designed and applied to the standard gate array wafer quickly and inexpensively as compared to the time and cost of developing a completely unique LSI circuit for the same overall function.
Gate arrays typically incorporate between one hundred to several thousand NOR or NAND gate circuits on a chip. These gate circuits are typically arranged in rows and columns. One advantage of gate arrays is that they can typically replace five to fifty separate small scale integration (SSI) and medium scale integration (MSI) chips. Moreover, implementing logic designs in gate arrays can lead to substantial reductions in (larger) physical size, (higher) power consumption, and total cost of a complete system. Furthermore, the reliability and high-speed performance of the integrated circuit may be improved because the number of off-chip connections is greatly decreased. Also, it is generally more difficult for a competitor to copy a product built using gate arrays than a product built from standard SS and MSI components.
When produced in large quantities, integrated circuits can be very economical. However, producing integrated circuits in low volume can be prohibitively expensive. Low volume runs are important for certain specialized applications and also for the intermediate development stage of integrated circuits that are eventually targeted for large volume production.
An industry has emerged to provide for relatively low-cost, easy to design, "semi" custom integrated circuits. These semi-custom circuits are also referred to as "application-specific integrated circuits" or ASICs. One of the earlier and still one of the most widely used types of ASIC is the CMOS gate array. A gate array, as will be explained in greater detail hereinafter, is an integrated circuit where the circuit elements (e.g., transistors) are predefined, and the interconnections between those circuit elements are not defined. Customization for specific applications is achieved by forming the interconnects between the circuit elements.
Since several different integrated circuit designs (i.e., logic designs) can be based upon the same base array, cost savings may be realized in the relatively high volume production of the base array. As will be explained in greater detail hereinafter, the customization also takes advantage of the economies of scale, since the different custom logic designs typically require only different contact and metalization masks. Accordingly, gate arrays provide many of the cost savings associated with large volume runs to small volume ASIC runs.
One of the problems that CMOS gate arrays share with other integrated circuits, is vulnerability to gate charge. During the process of building silicon wafers, there is a potential for damage to occur to the transistors during metalization. Metalization is the process when the transistors are connected together with metal layers to form the logic design. For example, the process of patterning the metal can cause excess electrical charge to build up on the gates of the transistors. During metalization, it is common to use ion beams to cut (or etch) metal. These ion beams deposit charges on the metal. These charges travel freely on the metal to damage the gate electrode of any transistor that is coupled to the metal.
Specifically, these charges build up on the polysilicon and cause charges to embed in the gate oxide layer that is below the polysilicon. This build up of charge in the gate oxide degrades transistor performance and reduces the effective life of a transistor. For example, charge build-up in the gate oxide may lead to gate leakage, which reduces the drive capacity of the transistor. Also, if the build-up of charge is large enough, it can cause permanent damage to the transistor
In a full-custom chip or a standard cell, the logic design is known, and problem nodes (e.g., nodes that may be susceptible to gate charge damage) are easily identified during the design phase. Protection for these nodes of transistors is designed for specifically in the layout. However, with a gate array, the logic function of the array or of each cell in the array is unknown until after the metal layers are added and the connections are made. In other words, in a gate array, each transistor requires protection since each transistor is susceptible to gate charge as the final logic design is unknown.
When the length of a metal trace between a drive transistor and the next transistor is greater than a predetermined trace length, this gate charge problem (also known as "floating gate" problem or the "node antenna" problem) arises. This problem arises when the drive transistor is coupled to the target transistor by employing two different metal layers (the floating gate problem).
If the length of metal trace that couples a drive transistor to a target transistor, which may need protection, is below a predetermined length this gate charge problem is not significant. Accordingly, one approach to solve the gate charge problem is to impose stringent layout rules that require the length of metal trace that couples a drive transistor to a target transistor to be less than a specified length. However, this layout rule is restrictive and at times impossible to meet while simultaneously meeting the performance and transistor density criteria of the integrated circuit.
A solution to this gate charge problem is to couple the gate electrode of the target transistor to a protection diode. As noted, this approach to the gate charge problem is of connecting the gate electrode of the target transistor to a protection device is appropriate when the gate electrode floats. The diode, which is used as a protection device, is specifically designed into the gate array. These diodes prevent charge build-up on the gate electrode of the target transistor.
For custom designs, this approach works relatively well because the problem transistors are generally known ahead of time. Therefore, not all transistors are exposed to this gate charge problem and accordingly do not require a protection diode.
However for gate arrays, since each transistor may be a target transistor, a protection diode would need to be designed into the integrated circuit for each transistor to insure protection, since the final design is not known.
This approach is wasteful of die area because the introduction of these diodes that include diffusion occupy additional area of the integrated circuit. For example, in certain designs, the use of diodes can occupy 30%-40% of the area of the gate array. Moreover, the introduction of these additional diffusion areas, by virtue of the layout rules, takes up additional area in addition to the actual diffusion area to meet these minimum distance requirements of the layout rule. Therefore, this approach wastes die area, increases the cost of the integrated circuit, and sacrifices transistor density. Accordingly, a method and apparatus for protecting the gate electrode of target transistors in a gate array that does not require the use of additional diffusion area and that reduces the cost and space consumption is desired.